网站重新上线，多谢朋友们的关心
Feb
14
参考资料：
UG070: Virtex 4 User Guide Chapter 6-8
Xapp705: Virtex-4 High-Speed Dual Data Rate LVDS Transceiver
Xapp707: Advanced ChipSync Applications application note
Xapp700: Dynamic Phase Alignment for Networking Applications
Xilinx Customer Training Course:
Design for Performance
Design with Virtex 4
UG070: Virtex 4 User Guide Chapter 6-8
Xapp705: Virtex-4 High-Speed Dual Data Rate LVDS Transceiver
Xapp707: Advanced ChipSync Applications application note
Xapp700: Dynamic Phase Alignment for Networking Applications
Xilinx Customer Training Course:
Design for Performance
Design with Virtex 4
Feb
7
Xilinx Answer Record 18181
Virtex-II/-II Pro/-4 - What are the rules for cascading two DCMs in series?
The recommendations for cascading DCMs are as follows:
- Do not cascade DCMs unless it is absolutely necessary; jitter accumulates when the DCMs are cascaded. Consequently, the output clock jitter of the second stage DCM is worse than the output clock jitter of the first stage DCM. If possible, implement your application using two DCMs in parallel instead of in series.
- Due to the accumulative nature of the DCM jitter, Xilinx does not recommend cascading CLKFX to CLKFX in high-frequency mode (see details below on how to calculate accumulative jitter).
- If the frequency of the DCM inputs allow it, use feedback for both DCMs.
- Use the inverted LOCKED of DCM1 to create reset of DCM2. For Virtex-II and Virtex-II Pro, the recommended length of a reset pulse is three CLKIN cycles. Consequently, Xilinx recommends using the inverted LOCKED of DCM1 as the input to an SRL16 and the output of the SRL16 as the reset input of DCM2. See the Virtex-4 Data Sheet for information on the minimum reset pulse required for the DCM.
- Use a dedicated clock line for CLKFX/CLK2X to CLKIN connection (i.e., through a BUFG).
- You are required to meet the input and output frequency and jitter specifications for each DCM.
- M/D ratio:
M and D values range per data sheet
R1 = M/D ratio for DCM1
R2 = M/D ratio for DCM2
Recommended: R1 > R2 (if possible)
- Jitter: the output jitter specifications for DLL outputs are provided in the data sheet. Use the Architecture Wizard to determine the jitter for CLKFX. Remember that Fin2 = Fin1 * M1 / D1, and then calculate the quadratic value. Jitter = Square Root (Jitter1*Jitter1 + Jitter2*Jitter2).
Cascading Example
Virtex-II/-II Pro/-4 - What are the rules for cascading two DCMs in series?
The recommendations for cascading DCMs are as follows:
- Do not cascade DCMs unless it is absolutely necessary; jitter accumulates when the DCMs are cascaded. Consequently, the output clock jitter of the second stage DCM is worse than the output clock jitter of the first stage DCM. If possible, implement your application using two DCMs in parallel instead of in series.
- Due to the accumulative nature of the DCM jitter, Xilinx does not recommend cascading CLKFX to CLKFX in high-frequency mode (see details below on how to calculate accumulative jitter).
- If the frequency of the DCM inputs allow it, use feedback for both DCMs.
- Use the inverted LOCKED of DCM1 to create reset of DCM2. For Virtex-II and Virtex-II Pro, the recommended length of a reset pulse is three CLKIN cycles. Consequently, Xilinx recommends using the inverted LOCKED of DCM1 as the input to an SRL16 and the output of the SRL16 as the reset input of DCM2. See the Virtex-4 Data Sheet for information on the minimum reset pulse required for the DCM.
- Use a dedicated clock line for CLKFX/CLK2X to CLKIN connection (i.e., through a BUFG).
- You are required to meet the input and output frequency and jitter specifications for each DCM.
- M/D ratio:
M and D values range per data sheet
R1 = M/D ratio for DCM1
R2 = M/D ratio for DCM2
Recommended: R1 > R2 (if possible)
- Jitter: the output jitter specifications for DLL outputs are provided in the data sheet. Use the Architecture Wizard to determine the jitter for CLKFX. Remember that Fin2 = Fin1 * M1 / D1, and then calculate the quadratic value. Jitter = Square Root (Jitter1*Jitter1 + Jitter2*Jitter2).
Cascading Example
Feb
5
Clock Jetter分为两种：Cycle-to-cycle Jitter和Period jitter。
Cycle-to-cycle Jitter：即每个clock cycle的差异。第一个输出是1000 ns，第二个是1001 ns，那么+1ns就是cycle2cycle了。Spartan3的DCM cycle-to-cycle是150~300ps
Period jitter 是Cycle-to-cycle 的一种总体的统计表现。
参考资料：
xapp462 [PDF]
Cycle-to-cycle Jitter：即每个clock cycle的差异。第一个输出是1000 ns，第二个是1001 ns，那么+1ns就是cycle2cycle了。Spartan3的DCM cycle-to-cycle是150~300ps
Period jitter 是Cycle-to-cycle 的一种总体的统计表现。
参考资料：
xapp462 [PDF]
Jan
17
1、用buffer_type约束。具体使用方法在XST User Guide
2、手动插入BUFG，然后设置允许使用BUFG的数量，那么手动插入的将拥有高优先级而先占用了BUFG。
2、手动插入BUFG，然后设置允许使用BUFG的数量，那么手动插入的将拥有高优先级而先占用了BUFG。
Jan
17
要更改所有IO Pin的IO Standard，可以打开PACE，选择所有管脚（通过shift或ctrl键多选），按右键，Create Constraints，然后自己选需要的吧：）
