网站重新上线，多谢朋友们的关心
Feb
16
从Xapp700中摘录的一段：（针对V4）
1、IDELAYCTRL模块是为了给tap delay line一个绝对的参考电压
2、每一个CLOCK REGION一个IDELAYCTRL
3、IDELAYCTRL的REFCLK需要一个200MHz时钟，占用全局时钟走线
4、IDELAYCTRL如果不加LOC约束，MAP就会启用并复制属性给所有的IDELAYCTRL，并在最后的RDY信号后加与门，这样会在每个CLOCK REGION都占用掉一个全局时钟走线（当然也有RST和RDY的走线）
关于IDELAYCTRL的更多信息，察看UG070
1、IDELAYCTRL模块是为了给tap delay line一个绝对的参考电压
2、每一个CLOCK REGION一个IDELAYCTRL
3、IDELAYCTRL的REFCLK需要一个200MHz时钟，占用全局时钟走线
4、IDELAYCTRL如果不加LOC约束，MAP就会启用并复制属性给所有的IDELAYCTRL，并在最后的RDY信号后加与门，这样会在每个CLOCK REGION都占用掉一个全局时钟走线（当然也有RST和RDY的走线）
关于IDELAYCTRL的更多信息，察看UG070
Dec
11
一片FPGA内使用多个DCM，时钟从一个clk输入，走到两个DCM的clk_in，然后让DCM操作。
这时，需要注意
1、用CoreGen生成DCM模块的时候，clk_in source是internal，不要他直接连接pin，加buffer。
2、手动例化一个IBUFG，然后把IBUFG的输入连接到两个DCM的clk_in
通常，如果没有设置clk_in source是internal，完全按照使用一个DCM的流程，就会造成clk_in multiple driver。
如果还想让这两个DCM输出的信号相位对齐，这个ISE是不能自动做到的。FPGA只能做到一个DCM的输出是相位对齐的。而时钟pin到两个DCM的路径和DCM输出的路径都有不同的延时，因此对相位还有要求可能就要自己手动调整DCM的位置了。
这时，需要注意
1、用CoreGen生成DCM模块的时候，clk_in source是internal，不要他直接连接pin，加buffer。
2、手动例化一个IBUFG，然后把IBUFG的输入连接到两个DCM的clk_in
通常，如果没有设置clk_in source是internal，完全按照使用一个DCM的流程，就会造成clk_in multiple driver。
如果还想让这两个DCM输出的信号相位对齐，这个ISE是不能自动做到的。FPGA只能做到一个DCM的输出是相位对齐的。而时钟pin到两个DCM的路径和DCM输出的路径都有不同的延时，因此对相位还有要求可能就要自己手动调整DCM的位置了。
Oct
12
在xapp463中有这么一节，介绍怎么用blockram实现逻辑功能，因为Blockram其实可以看作是一个很大的LUT+FF。
英文原文摘录如下：
Inside every Spartan-3 logic cell, there is a four-input RAM/ROM called a look-up table or LUT.
The LUT performs any possible logic function of its four inputs and forms the basis of the
Spartan-3 logic architecture.
Another possible application for block RAM is as a much larger look-up table. In one of its
organizations, a block RAM—used as ROM in this case—has 14 inputs and a single output.
Consequently, block RAM is capable of implementing any possible arbitrary logic function of up
to 14 inputs, regardless of the complexity and regardless of inversions. There are a few
restrictions, however.
• There cannot be any asynchronous feedback paths in the logic, such as those that create
latches.
• The logic output must be synchronized to a clock input. Block RAM does not support
asynchronous read outputs.
If the logic function meets these requirements, then a single block RAM implements the
following functions.
• Any possible Boolean logic function of up to 14 inputs
• Nine separate arbitrary Boolean logic functions of 11 inputs, as long as the inputs are
shared.
• Various other combinations are possible, but may have restrictions to the number of
inputs, the number of shared inputs, or the complexity of the logic function.
Due to the flexibility and speed of CLB logic, block RAM may not be faster or more efficient for
simple wide functions like an address decoder, where multiple inputs are ANDed together.
Block RAM will be faster and more efficient for complex logic functions, such as majority
decoders, pattern matching, correlators.
实现这个功能，需要用到map的-bp功能
Mapping Logic into Block RAM Using MAP –bp Option
The Xilinx ISE software does not automatically attempt to map logic functions into block RAM.
However, there is a mapping option to aid the process.
The block RAM mapping option is enabled when using the MAP –bp option. If so enabled, the
Xilinx ISE logic mapping software attempts to place LUTs and attached flip-flops into an
unused single-output, single-port block RAM. The final flip-flop output is required as block
RAMs have a synchronous, registered output. The mapping software packs the flip-flop with
whatever LUT logic is driving it. No register will be packed into block RAM without LUT logic,
and vice versa.
To specify which register outputs will be converted to block RAM outputs, create a file
containing a list of the net names connected to the register output(s). Set the environment
variable XIL_MAP_BRAM_FILE to the file name, which instructs the mapping software to use
this file. The MAP program looks for this environment variable whenever the –bp option is
specified. Only those output nets listed in the file are converted into block RAM outputs.
• PCs:
set XIL_MAP_BRAM_FILE=file_name
• Workstations:
setenv XIL_MAP_BRAM_FILE file_name
找时间做个test project:)
英文原文摘录如下：
Inside every Spartan-3 logic cell, there is a four-input RAM/ROM called a look-up table or LUT.
The LUT performs any possible logic function of its four inputs and forms the basis of the
Spartan-3 logic architecture.
Another possible application for block RAM is as a much larger look-up table. In one of its
organizations, a block RAM—used as ROM in this case—has 14 inputs and a single output.
Consequently, block RAM is capable of implementing any possible arbitrary logic function of up
to 14 inputs, regardless of the complexity and regardless of inversions. There are a few
restrictions, however.
• There cannot be any asynchronous feedback paths in the logic, such as those that create
latches.
• The logic output must be synchronized to a clock input. Block RAM does not support
asynchronous read outputs.
If the logic function meets these requirements, then a single block RAM implements the
following functions.
• Any possible Boolean logic function of up to 14 inputs
• Nine separate arbitrary Boolean logic functions of 11 inputs, as long as the inputs are
shared.
• Various other combinations are possible, but may have restrictions to the number of
inputs, the number of shared inputs, or the complexity of the logic function.
Due to the flexibility and speed of CLB logic, block RAM may not be faster or more efficient for
simple wide functions like an address decoder, where multiple inputs are ANDed together.
Block RAM will be faster and more efficient for complex logic functions, such as majority
decoders, pattern matching, correlators.
实现这个功能，需要用到map的-bp功能
Mapping Logic into Block RAM Using MAP –bp Option
The Xilinx ISE software does not automatically attempt to map logic functions into block RAM.
However, there is a mapping option to aid the process.
The block RAM mapping option is enabled when using the MAP –bp option. If so enabled, the
Xilinx ISE logic mapping software attempts to place LUTs and attached flip-flops into an
unused single-output, single-port block RAM. The final flip-flop output is required as block
RAMs have a synchronous, registered output. The mapping software packs the flip-flop with
whatever LUT logic is driving it. No register will be packed into block RAM without LUT logic,
and vice versa.
To specify which register outputs will be converted to block RAM outputs, create a file
containing a list of the net names connected to the register output(s). Set the environment
variable XIL_MAP_BRAM_FILE to the file name, which instructs the mapping software to use
this file. The MAP program looks for this environment variable whenever the –bp option is
specified. Only those output nets listed in the file are converted into block RAM outputs.
• PCs:
set XIL_MAP_BRAM_FILE=file_name
• Workstations:
setenv XIL_MAP_BRAM_FILE file_name
找时间做个test project:)
