网站重新上线，多谢朋友们的关心
Jun
20
目的：测试XST的复制寄存器功能
平台：ISE 9.1.02
结果：没有实现自动复制寄存器。XST总是插入Buffer。看来要复制还得手动。
文件：VHDL，截图和结果报告。
下载文件
后续：有知道怎样让XST自动复制寄存器的（对于指定net）请给我留言。
平台：ISE 9.1.02
结果：没有实现自动复制寄存器。XST总是插入Buffer。看来要复制还得手动。
文件：VHDL，截图和结果报告。
下载文件 后续：有知道怎样让XST自动复制寄存器的（对于指定net）请给我留言。
May
14
ISE6以前： Xilinx Answer Record 19604
ISE7以后： Xilinx Answer Record 21508
ISE9的compxlib已经有图形界面，就更方便了一些。Xilinx Answer Record 24800
修改了ModelSim.ini后，要注意这个ini是不是真正起作用，因为modelsim有比安装目录中的优先级更高的modelsim.ini，他们分别是工程目录中的modelsim.ini和在环境变量MODELSIM中指定的modelsim.ini。
ISE7以后： Xilinx Answer Record 21508
ISE9的compxlib已经有图形界面，就更方便了一些。Xilinx Answer Record 24800
修改了ModelSim.ini后，要注意这个ini是不是真正起作用，因为modelsim有比安装目录中的优先级更高的modelsim.ini，他们分别是工程目录中的modelsim.ini和在环境变量MODELSIM中指定的modelsim.ini。
Mar
29
Xapp251: Hot-Swapping Virtex-II and Virtex-II Pro Devices
Answer Record 19777: Are Spartan-3/-3E devices hot-swappable?
Answer Record 19777: Are Spartan-3/-3E devices hot-swappable?
Feb
14
参考资料：
UG070: Virtex 4 User Guide Chapter 6-8
Xapp705: Virtex-4 High-Speed Dual Data Rate LVDS Transceiver
Xapp707: Advanced ChipSync Applications application note
Xapp700: Dynamic Phase Alignment for Networking Applications
Xilinx Customer Training Course:
Design for Performance
Design with Virtex 4
UG070: Virtex 4 User Guide Chapter 6-8
Xapp705: Virtex-4 High-Speed Dual Data Rate LVDS Transceiver
Xapp707: Advanced ChipSync Applications application note
Xapp700: Dynamic Phase Alignment for Networking Applications
Xilinx Customer Training Course:
Design for Performance
Design with Virtex 4
Feb
7
Xilinx Answer Record 18181
Virtex-II/-II Pro/-4 - What are the rules for cascading two DCMs in series?
The recommendations for cascading DCMs are as follows:
- Do not cascade DCMs unless it is absolutely necessary; jitter accumulates when the DCMs are cascaded. Consequently, the output clock jitter of the second stage DCM is worse than the output clock jitter of the first stage DCM. If possible, implement your application using two DCMs in parallel instead of in series.
- Due to the accumulative nature of the DCM jitter, Xilinx does not recommend cascading CLKFX to CLKFX in high-frequency mode (see details below on how to calculate accumulative jitter).
- If the frequency of the DCM inputs allow it, use feedback for both DCMs.
- Use the inverted LOCKED of DCM1 to create reset of DCM2. For Virtex-II and Virtex-II Pro, the recommended length of a reset pulse is three CLKIN cycles. Consequently, Xilinx recommends using the inverted LOCKED of DCM1 as the input to an SRL16 and the output of the SRL16 as the reset input of DCM2. See the Virtex-4 Data Sheet for information on the minimum reset pulse required for the DCM.
- Use a dedicated clock line for CLKFX/CLK2X to CLKIN connection (i.e., through a BUFG).
- You are required to meet the input and output frequency and jitter specifications for each DCM.
- M/D ratio:
M and D values range per data sheet
R1 = M/D ratio for DCM1
R2 = M/D ratio for DCM2
Recommended: R1 > R2 (if possible)
- Jitter: the output jitter specifications for DLL outputs are provided in the data sheet. Use the Architecture Wizard to determine the jitter for CLKFX. Remember that Fin2 = Fin1 * M1 / D1, and then calculate the quadratic value. Jitter = Square Root (Jitter1*Jitter1 + Jitter2*Jitter2).
Cascading Example
Virtex-II/-II Pro/-4 - What are the rules for cascading two DCMs in series?
The recommendations for cascading DCMs are as follows:
- Do not cascade DCMs unless it is absolutely necessary; jitter accumulates when the DCMs are cascaded. Consequently, the output clock jitter of the second stage DCM is worse than the output clock jitter of the first stage DCM. If possible, implement your application using two DCMs in parallel instead of in series.
- Due to the accumulative nature of the DCM jitter, Xilinx does not recommend cascading CLKFX to CLKFX in high-frequency mode (see details below on how to calculate accumulative jitter).
- If the frequency of the DCM inputs allow it, use feedback for both DCMs.
- Use the inverted LOCKED of DCM1 to create reset of DCM2. For Virtex-II and Virtex-II Pro, the recommended length of a reset pulse is three CLKIN cycles. Consequently, Xilinx recommends using the inverted LOCKED of DCM1 as the input to an SRL16 and the output of the SRL16 as the reset input of DCM2. See the Virtex-4 Data Sheet for information on the minimum reset pulse required for the DCM.
- Use a dedicated clock line for CLKFX/CLK2X to CLKIN connection (i.e., through a BUFG).
- You are required to meet the input and output frequency and jitter specifications for each DCM.
- M/D ratio:
M and D values range per data sheet
R1 = M/D ratio for DCM1
R2 = M/D ratio for DCM2
Recommended: R1 > R2 (if possible)
- Jitter: the output jitter specifications for DLL outputs are provided in the data sheet. Use the Architecture Wizard to determine the jitter for CLKFX. Remember that Fin2 = Fin1 * M1 / D1, and then calculate the quadratic value. Jitter = Square Root (Jitter1*Jitter1 + Jitter2*Jitter2).
Cascading Example
