Cascade DCM in FPGA
IDELAYCTRL
Feb
14
ChipSync - SERDES IDELAY BITSLIP 
参考资料：
UG070: Virtex 4 User Guide Chapter 6-8
Xapp705: Virtex-4 High-Speed Dual Data Rate LVDS Transceiver
Xapp707: Advanced ChipSync Applications application note
Xapp700: Dynamic Phase Alignment for Networking Applications
Xilinx Customer Training Course:
Design for Performance
Design with Virtex 4
UG070: Virtex 4 User Guide Chapter 6-8
Xapp705: Virtex-4 High-Speed Dual Data Rate LVDS Transceiver
Xapp707: Advanced ChipSync Applications application note
Xapp700: Dynamic Phase Alignment for Networking Applications
Xilinx Customer Training Course:
Design for Performance
Design with Virtex 4
