FPGA Notes

   <FSM_NAME>_SYNC_PROC: process (<clock>)
   begin
      if (<clock>'event and <clock> = '1') then
         if (<reset> = '1') then
            <fsm>_state <= st1_<name_state>;
            -- Output signals here will have one clock delay of the <state>
            <output1> <= '0';
            <output2> <= '0';

         else
            <fsm>_state <= <fsm>_next_state;
            <output1> <= <output1>_c;
            <output2> <= <output2>_c;

         -- assign other outputs to internal signals

         end if;        
      end if;
   end process;


   <FSM_NAME>_NEXT_STATE_DECODE: process (<fsm>_state, <input1>, <input2>, ...)
   begin
      --declare default state for next_state to avoid latches
      <fsm>_next_state <= <fsm>_state;  
      -- default is to stay in current state
      -- so there are no else branch in the if statement
      case (<fsm>_state) is
         when <fsm>_st1_<name> =>
            -- State Change Condition
            if <input_1> = '1' then
               <fsm>_next_state <= <fsm>_st2_<name>;
               -- Internal Output can put here
               -- Only occur on state transaction (next_state changed but state not changed)
               -- If output need to assert at first cycle of one state,
               -- we can delay this output one clock in <FSM_NAME>_SYNC_PROC process
            end if;
            -- Internal Output can put here
            -- This output will be asserted till state change

         when <fsm>_st2_<name> =>
            if <input_2> = '1' then
               <fsm>_next_state <= <fsm>_st3_<name>;
            end if;
         when <fsm>_st3_<name> =>
            <fsm>_next_state <= <fsm>_st1_<name>;
         when others =>
            <fsm>_next_state <= <fsm>_st1_<name>;
      end case;      
   end process;