Oct
19
手上有一批设计想测试性能，一个一个点综合，布局布线很麻烦，而且占用资源，想写个script让他晚上跑。想到了XFlow，兴致勃勃地看帮助文档，做试验，结果，XFlow让我失望了。
首先是用XST，如果用-synth xst_verilog.opt，就会报错
Compiling verilog file "F:\CASE\Simon\open_source\open_aes\xflow/open_aes.prj" i
n library work
ERROR:HDLCompilers:26 - "F:\CASE\Simon\open_source\open_aes\xflow/open_aes.prj"
line 1 expecting 'EOF', found 'verilog'
Analysis of file <"F:\CASE\Simon\open_source\open_aes\xflow/open_aes.prj"> faile
d.
奇怪伐，竟然第一行expecting 'EOF'！我无语了。
Workaround:用xst_mixed.opt就可以
接下来的事情还要郁闷，用synplify_pro综合，总是找不到architecture, part等等，以至于完全不能实现了。
我还是老老实实用手点得了-_-bb
首先是用XST，如果用-synth xst_verilog.opt，就会报错
Compiling verilog file "F:\CASE\Simon\open_source\open_aes\xflow/open_aes.prj" i
n library work
ERROR:HDLCompilers:26 - "F:\CASE\Simon\open_source\open_aes\xflow/open_aes.prj"
line 1 expecting 'EOF', found 'verilog'
Analysis of file <"F:\CASE\Simon\open_source\open_aes\xflow/open_aes.prj"> faile
d.
奇怪伐，竟然第一行expecting 'EOF'！我无语了。
Workaround:用xst_mixed.opt就可以
接下来的事情还要郁闷，用synplify_pro综合，总是找不到architecture, part等等，以至于完全不能实现了。
我还是老老实实用手点得了-_-bb
Oct
18
昨天在Michael的指引下玩了一下403的板子，大为崇拜做板子的和写Reference Design的大牛。
403的板子，不仅运行了Microblaze和PowerPC，还移植了MontaVista Linux和QNX，牛气冲天阿：）
403的板子，不仅运行了Microblaze和PowerPC，还移植了MontaVista Linux和QNX，牛气冲天阿：）
Oct
13
所谓Tips，总是借鉴一点别人的东西，不过，只写我觉得对我有用的Tips
1、Outlook回复引用变为英文（比如把回复写成RE，对在外企工作的很有用）
outlook 工具 --> 选项 --> 邮件选项 --> 国际选项
2、Outlook实现与Gmail类似的列出所有相关邮件
邮件列表选中邮件，查找全部 --> 相关邮件
虽然有点麻烦，但是能实现这个功能还算不错了
3、将接收邮件显示为Txt
outlook工具 --> 选项 --> 首选参数 --> 电子邮件选项 --> 以纯文本形式显示所有邮件
这样做是因为，HTML显示方式不能改变字体大小，TXT方式则只需要按CTRL和鼠标滚轮就可以把字体设置成最舒服的大小了。同样，我也喜欢写邮件时只写纯文本格式的邮件。
4、为邮件添加注释
将邮件拖曳至便签，添加注释即可。虽然不是很直接的方式，不过能看到自己所有的注释，并且能够用过查找工具搜索到，也已经不错了。
5、Excel怎么实现表头固定，内容滚动？
在Excel表格中，通常如果表格内容很长，将内容滚动时，表头就看不见了，每列的名字也就看不见了，一些数据容易混淆。Excel有一个功能可以实现表头固定，仅滚动内容。实现方法是先选中内容的起始行，然后选择菜单：窗口->冻结窗口
6、将邮件定时发送
撰写好的邮件，如果不想立即发送出去，而是希望在日后的某个特定时间内发送的话，这时该怎么办呢？其实很简单，我们可以如下来设置：在邮件编辑窗口中，单击工具栏上的“选项”按钮，打开“邮件选项”对话框，然后勾中“传递不早于”一项，并设定好具体的日期和时间即可。这样一来，系统则会自动根据设定的时间来选择发送邮件的时机了。
7. 写论文时常用的Word技巧
http://www.rickysu.com/bo/word_tips/
8. Outlook插件
Xobni是一个很不错的插件，方便搜索信息。
9. 将整封邮件的Title显示有颜色，而不仅仅是添加标签
查看“工具 --> 组织”。我会把老板的信建标记为红色
10. 阅读N秒后自动将邮件标记为已读
工具-->选项-->其他-->阅读窗格-->N秒后标记为已读
1、Outlook回复引用变为英文（比如把回复写成RE，对在外企工作的很有用）
outlook 工具 --> 选项 --> 邮件选项 --> 国际选项
2、Outlook实现与Gmail类似的列出所有相关邮件
邮件列表选中邮件，查找全部 --> 相关邮件
虽然有点麻烦，但是能实现这个功能还算不错了
3、将接收邮件显示为Txt
outlook工具 --> 选项 --> 首选参数 --> 电子邮件选项 --> 以纯文本形式显示所有邮件
这样做是因为，HTML显示方式不能改变字体大小，TXT方式则只需要按CTRL和鼠标滚轮就可以把字体设置成最舒服的大小了。同样，我也喜欢写邮件时只写纯文本格式的邮件。
4、为邮件添加注释
将邮件拖曳至便签，添加注释即可。虽然不是很直接的方式，不过能看到自己所有的注释，并且能够用过查找工具搜索到，也已经不错了。
5、Excel怎么实现表头固定，内容滚动？
在Excel表格中，通常如果表格内容很长，将内容滚动时，表头就看不见了，每列的名字也就看不见了，一些数据容易混淆。Excel有一个功能可以实现表头固定，仅滚动内容。实现方法是先选中内容的起始行，然后选择菜单：窗口->冻结窗口
6、将邮件定时发送
撰写好的邮件，如果不想立即发送出去，而是希望在日后的某个特定时间内发送的话，这时该怎么办呢？其实很简单，我们可以如下来设置：在邮件编辑窗口中，单击工具栏上的“选项”按钮，打开“邮件选项”对话框，然后勾中“传递不早于”一项，并设定好具体的日期和时间即可。这样一来，系统则会自动根据设定的时间来选择发送邮件的时机了。
7. 写论文时常用的Word技巧
http://www.rickysu.com/bo/word_tips/
8. Outlook插件
Xobni是一个很不错的插件，方便搜索信息。
9. 将整封邮件的Title显示有颜色，而不仅仅是添加标签
查看“工具 --> 组织”。我会把老板的信建标记为红色
10. 阅读N秒后自动将邮件标记为已读
工具-->选项-->其他-->阅读窗格-->N秒后标记为已读
Oct
12
在xapp463中有这么一节，介绍怎么用blockram实现逻辑功能，因为Blockram其实可以看作是一个很大的LUT+FF。
英文原文摘录如下：
Inside every Spartan-3 logic cell, there is a four-input RAM/ROM called a look-up table or LUT.
The LUT performs any possible logic function of its four inputs and forms the basis of the
Spartan-3 logic architecture.
Another possible application for block RAM is as a much larger look-up table. In one of its
organizations, a block RAM—used as ROM in this case—has 14 inputs and a single output.
Consequently, block RAM is capable of implementing any possible arbitrary logic function of up
to 14 inputs, regardless of the complexity and regardless of inversions. There are a few
restrictions, however.
• There cannot be any asynchronous feedback paths in the logic, such as those that create
latches.
• The logic output must be synchronized to a clock input. Block RAM does not support
asynchronous read outputs.
If the logic function meets these requirements, then a single block RAM implements the
following functions.
• Any possible Boolean logic function of up to 14 inputs
• Nine separate arbitrary Boolean logic functions of 11 inputs, as long as the inputs are
shared.
• Various other combinations are possible, but may have restrictions to the number of
inputs, the number of shared inputs, or the complexity of the logic function.
Due to the flexibility and speed of CLB logic, block RAM may not be faster or more efficient for
simple wide functions like an address decoder, where multiple inputs are ANDed together.
Block RAM will be faster and more efficient for complex logic functions, such as majority
decoders, pattern matching, correlators.
实现这个功能，需要用到map的-bp功能
Mapping Logic into Block RAM Using MAP –bp Option
The Xilinx ISE software does not automatically attempt to map logic functions into block RAM.
However, there is a mapping option to aid the process.
The block RAM mapping option is enabled when using the MAP –bp option. If so enabled, the
Xilinx ISE logic mapping software attempts to place LUTs and attached flip-flops into an
unused single-output, single-port block RAM. The final flip-flop output is required as block
RAMs have a synchronous, registered output. The mapping software packs the flip-flop with
whatever LUT logic is driving it. No register will be packed into block RAM without LUT logic,
and vice versa.
To specify which register outputs will be converted to block RAM outputs, create a file
containing a list of the net names connected to the register output(s). Set the environment
variable XIL_MAP_BRAM_FILE to the file name, which instructs the mapping software to use
this file. The MAP program looks for this environment variable whenever the –bp option is
specified. Only those output nets listed in the file are converted into block RAM outputs.
• PCs:
set XIL_MAP_BRAM_FILE=file_name
• Workstations:
setenv XIL_MAP_BRAM_FILE file_name
找时间做个test project:)
英文原文摘录如下：
Inside every Spartan-3 logic cell, there is a four-input RAM/ROM called a look-up table or LUT.
The LUT performs any possible logic function of its four inputs and forms the basis of the
Spartan-3 logic architecture.
Another possible application for block RAM is as a much larger look-up table. In one of its
organizations, a block RAM—used as ROM in this case—has 14 inputs and a single output.
Consequently, block RAM is capable of implementing any possible arbitrary logic function of up
to 14 inputs, regardless of the complexity and regardless of inversions. There are a few
restrictions, however.
• There cannot be any asynchronous feedback paths in the logic, such as those that create
latches.
• The logic output must be synchronized to a clock input. Block RAM does not support
asynchronous read outputs.
If the logic function meets these requirements, then a single block RAM implements the
following functions.
• Any possible Boolean logic function of up to 14 inputs
• Nine separate arbitrary Boolean logic functions of 11 inputs, as long as the inputs are
shared.
• Various other combinations are possible, but may have restrictions to the number of
inputs, the number of shared inputs, or the complexity of the logic function.
Due to the flexibility and speed of CLB logic, block RAM may not be faster or more efficient for
simple wide functions like an address decoder, where multiple inputs are ANDed together.
Block RAM will be faster and more efficient for complex logic functions, such as majority
decoders, pattern matching, correlators.
实现这个功能，需要用到map的-bp功能
Mapping Logic into Block RAM Using MAP –bp Option
The Xilinx ISE software does not automatically attempt to map logic functions into block RAM.
However, there is a mapping option to aid the process.
The block RAM mapping option is enabled when using the MAP –bp option. If so enabled, the
Xilinx ISE logic mapping software attempts to place LUTs and attached flip-flops into an
unused single-output, single-port block RAM. The final flip-flop output is required as block
RAMs have a synchronous, registered output. The mapping software packs the flip-flop with
whatever LUT logic is driving it. No register will be packed into block RAM without LUT logic,
and vice versa.
To specify which register outputs will be converted to block RAM outputs, create a file
containing a list of the net names connected to the register output(s). Set the environment
variable XIL_MAP_BRAM_FILE to the file name, which instructs the mapping software to use
this file. The MAP program looks for this environment variable whenever the –bp option is
specified. Only those output nets listed in the file are converted into block RAM outputs.
• PCs:
set XIL_MAP_BRAM_FILE=file_name
• Workstations:
setenv XIL_MAP_BRAM_FILE file_name
找时间做个test project:)
Oct
12
如果写了一个component有两个architecture，要选择结构体，那么需要用configuration语句：
在声明好Component后，加一句for语句在所有的声明后面（包括signal的声明），begin的前面（Architecture对应的那个Begin）
For Instance_name : component_name USE Entity WORK.entity_name(architecture_name);
其中entity_name其实就是前面对应的component_name
更详细的，可以参考XST User Guide，在文档中查找"component configuration"
在声明好Component后，加一句for语句在所有的声明后面（包括signal的声明），begin的前面（Architecture对应的那个Begin）
For Instance_name : component_name USE Entity WORK.entity_name(architecture_name);
其中entity_name其实就是前面对应的component_name
更详细的，可以参考XST User Guide，在文档中查找"component configuration"
