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<title><![CDATA[FPGA Notes]]></title> 
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<description><![CDATA[Learning Notes about Xilinx FPGA, ISE, EDK and IC Industry]]></description> 
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<copyright><![CDATA[FPGA Notes]]></copyright>
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<link>http://www.fpganotes.com/post/87/</link>
<title><![CDATA[用什么查看EDIF网表？]]></title> 
<author>RickySu &lt;sutongqi+blog@gmail.com&gt;</author>
<category><![CDATA[技术经验]]></category>
<pubDate>Wed, 31 Jan 2007 04:44:57 +0000</pubDate> 
<guid>http://www.fpganotes.com/post/87/</guid> 
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<![CDATA[ 
	1. GateVision<br/>2. Synplify_pro<br/>3. Xilinx PlanAhead<br/>Tags - <a href="http://www.fpganotes.com/tags/planahead/" rel="tag">planahead</a> , <a href="http://www.fpganotes.com/tags/edif/" rel="tag">edif</a>
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<link>http://www.fpganotes.com/post/87/#blogcomment104</link>
<title><![CDATA[[评论] 用什么查看EDIF网表？]]></title> 
<author>thx &lt;user@domain.com&gt;</author>
<category><![CDATA[评论]]></category>
<pubDate>Mon, 16 Mar 2009 07:46:34 +0000</pubDate> 
<guid>http://www.fpganotes.com/post/87/#blogcomment104</guid> 
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<![CDATA[ 
	博主请问1 GateVision是什么啊，还有我现在综合就用XST，不想用Synplify_pro了，那么看来我想看网表只有第三条路了，那么PlanAhead有什么器件限制吗，v2p支持吗<br/>谢谢哦
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