xdl -ncd2xdl xx.ncd

(* RLOC = "X1Y2" *)
reg e_reg;

(* RLOC = "X0Y1" *)
FDCPE #(
      .INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
   ) FDCPE_a (
      .Q(a_reg),      // Data output
      .C(clk),      // Clock input
      .CE(1'b1),    // Clock enable input
      .CLR(reset),  // Asynchronous clear input
      .D(a),      // Data input
      .PRE(1'b0)   // Asynchronous set input
   );

•   The software stores the transmit data in the dual port memory starting at address offset 0x0
•   The software writes the length data in the dual port memory at address offset 0x07F4
•   The software writes a ’1’ to the Status bit at address offset 0x07FC (bit 31 on the data bus)
•   The software monitors the Status bit and waits until it is set to ’0’ by the Ethernet Lite MAC before initiating another transmit
•   If the transmit interrupt and the global interrupt are both enabled, an interrupt will occur when the Ethernet Lite MAC clears the Status bit
•   The transmit interrupt if enabled will also occur with the completion on writing the MAC address

Generate the preamble and start of frame fields
•   Read the length and the specified amount of data out of the dual port memory according to the length value adding padding if required
•   Detect any collision and performing any jamming, backoff, and retry if necessary
•   Calculates the CRC and appends it to the end of the data
•   Clears the status bit at the completion of the transmission
•   Clearing the status bit will cause a transmit complete interrupt if enabled